1. Field of the Invention
The invention is directed to a method and resulting integrated circuit for the manufacture of field effect transistors that is useful in the micron and submicron technology and more particularly to the use of a preferential oxidation technique to allow the formation of self-aligned contacts to designated source/drain regions.
2. Description of the Prior Art
Self-aligned contact processes are very desirable, because they reduce mask steps and more importantly prevent the misalignment due to lithography. This misalignment can cause product defects and yield loss. The normal way to overcome the misalignment problem is to give a greater mask tolerance. However, as design rules and feature sizes are reduced to submicron dimensions, this greater mask tolerance solution becomes a disadvantage.
It is generally known in the art that certain types of silicon doping can cause different thermally grown silicon oxide thickness. References that show this are Bruchez U.S. Pat. No. 3,886,004; Esch et al U.S. Pat. No. 3,899,372; Owen U.S. Pat. No. 4,026,740; Iwai U.S. Pat. No. 4,327,476; Havemann U.S. Pat. No. 4,635,344; Mass et al U.S. Pat. No. 4,659,428; and Verma U.S. Pat. No. 4,717,687. None of these references teach or suggest the present self-aligned contact technology of this invention.
The use of titanium nitride, titanium tungsten or the like as a metallurgy for integrated circuits is known. Also, misalignment problems are known and many solutions have been proposed. Examples of titanium nitride and the like include Jopke, Jr. et al U.S. Pat. No. 4,486,946; Holloway et al U.S. Pat. No. 4,657,628; Orban U.S. Pat. No. 4,745,089; Groover, III et al U.S. Pat. No. 4,804,636; Pintchovski et al U.S. Pat. No. 4,822,753; and Kim et al U.S. Pat. No. 4,845,050. Examples of misalignment solutions are Reynolds et al U.S. Pat. No. 4,381,215; Courreges U.S. Pat. No. 4,392,150; and Aboelfotoh et al U.S. Pat. No. 4,888,297. However, the particular use of this metallurgy and alignment solutions are different from and do not suggest that described in the present invention.
The use of titanium silicide as a contact metallurgy is also known and can be seen in, for example Scovell et al U.S. Pat. No. 4,468,308; Anderson U.S. Pat. No. 4,751,198; Anderson U.S. Pat. No. 4,589,196; Pintchovski U.S. Pat. No. 4,619,038; Scovell et al U.S. Pat. No. 4,772,571; Deneuville et al U.S. Pat. No. 4,777,150; Stevens et al U.S. Pat. No. 4,784,973; and Flanner et al U.S. Pat. No. 4,822,749. The particular process and resulting integrated circuit is not described or suggested by any of these references.
It is therefore a principal object of this invention to describe a process that uses preferential oxidation in the manufacture of MOS field effect transistor integrated circuits to form self-aligned contacts to certain designated source/drain.